1. Field of the Invention
The present invention relates to a structure of semiconductor device and a method for fabricating the same. More particularly, the present invention relates to a dual damascene structure and a method for fabricating the same.
2. Description of the Related Art
Currently, dual damascene techniques are widely used to embed metal inter-connect structures in insulating layers. By using dual damascene methods, the overlay errors and the process biases between metal contacts and lines can be reduced, as compared with the conventional method that forms a metal contact first and then directly defines a metal line. Consequently, the reliability and throughput of products can be improved. Hence, dual damascene techniques are very important in advanced semiconductor processes where devices are highly integrated.
In some dual damascene methods, the trench is defined with a hard mask layer with a trench pattern therein, and the contact hole is defined with a patterned photoresist layer with a contact-hole pattern therein that is formed after the hard mask layer. However, when misalignment occurs between the trench pattern and the contact-hole pattern such that the contact-hole pattern exposes a portion of the hard mask layer, the etching step of the contact hole is restricted by the hard mask layer to reduce the cross-sectional area of the contact hole. Therefore, the cross-sectional area of the contact formed later is also reduced, so that the contact resistance is raised to lower the speed of the device or even decrease the yield of the process.